Journal Papers
[1] I. Milentijevic, V. Ciric, O. Vojinovic: “ VERSION CONTROL IN PROJECT-BASED LEARNING” , Computers&Education, An Internation Journal , Elsevier Science, 2007. ( accepted for publication ).
[2] V. Ciric, I. Milentijevic “ Configurable Folded Array for FIR Filtering ” , Journal of Systems Architecture , Elsevier Science, 2007. ( accepted for publication ).
[3] I.Z.Milentijevic, M.K.Stojcev, D.M.Maksimovic, "CONFIGURABLE DIGIT-SERIAL CONVOLVER OF TYPE F", Microelectronics Journal , Vol. 27, No 6, pp. 559-566, September 1996.
[4] I.Z.Milentijevic, I.Z.Milovanovic, E.I.Milovanovic, M.B.Tošic, M.K.Stojcev, "TWO-LEVEL PIPELINED SYSTOLIC ARRAYS FOR MATRIX-VECTOR MULTIPLICATION ", Journal of Systems Architecture, The Euromicro Journal, Vol. 44, No. 5, pp. 383-388, 1998.
[5] I.Z.Milentijevic, I.Ž.Milovanovic, E.I.Milovanovic, M.K.Stojcev, “THE DESIGN OF OPTIMAL PLANAR SYSTOLIC ARRAYS FOR MATRIX MULTIPLICATION”, Computers Mat. Applic., Vol. 33, No. 6, pp.17-35, 1997.
[6] I.Ž.Milovanovic, E.I.Milovanovic, I.Z.Milentijevic, M.K.Stojcev, "DESIGNING OF PROCESSOR-TIME OPTIMAL SYSTOLIC ARRAYS FOR BAND MATRIX-VECTOR MULTIPLICATION", Computers Math. Applic. , Vol. 32, No. 2, pp. 21-31, 1996.
[7] I. Milentijevic, V. Ciric, O. Vojinovic and T. Tokic: “ Folded Semi-Systolic FIR Filter Architecture with Changeable Folding Factor”, Neural, Parallel & Scientific Computations, Vol. 10, No 2, Dynamic Publishers Atlanta, USA, June 2002, pp. 235-248.
[8] E.I.Milovanovic, I.Z.Milentijevic, I.Ž.Milovanovic, “DESIGNING OF PROCESSOR-TIME OPTIMAL HEXAGONAL SYSTOLIC ARRAY FOR MATRIX MULTIPLICATION”, Computers and Artificial Intelligence , Vol. 16, No. 1, pp. 1-11, 1997.
[9] M. Stojcev, I.Z. Milentijevic , D. Kehagias, R. Drechsler, M. Gusev, "COMPUTER ARCHITECTURE CORE OF KNOWLEDGE FOR COMPUTER SCIENCE STUDIES", Computer Society Journal , Volume I, Edition 4 April 2003, pp. 42-45.
[10] I.Z.Milentijevic, M.K.Stojcev, D.M.Maksimovic, "DIGIT-SERIAL SEMI-SYSTOLIC CONVOLVER", Facta Universitatis, Niš, Ser. Elec. Energ., Vol. 8, No 2, pp. 191-210, 1995.
[11] M.B.Tošicc, I.Z.Milentijevic, E.I.Milovanovic, "UNIDIRECTIONAL TWO-WAY PIPELINED LINEAR SYSTOLIC ARRAY FOR MATRIX-VECTOR MULTIPLICATION", Facta Universitatis, Niš, Ser. Math. Inform. , No. 11, pp. 129-142, 1996.
[12] I. Z. Milentijevic, V. Ciric, T. Tokic and O. Vojinovic: “ FPGA Implementation of Folded FIR Filter Architecture with Changeable Folding Factor”, Facta Universitatis , Ser. Electronics and Energetics, Vol. 15, No 3, December 2002, pp. 451-464.
[13] T. Tokic, I. Z. Milentijevic, M. Stojcev, O. Vojinovic, A.Vucetic: “ IMPLEMENTATION OF STUDENT MOBILITY PROGRAM WITHIN THE FRAME OF TEMPUS PROJECT CD-JEP 16160/2001”, Facta Universitatis , Ser. Electronics and Energetics, Vol. 18, No 2, August 2005, pp. 345-352.
[14] O. Vojinovic, I. Z. Milentijevic: “ PRESENTATION AND SIMULATION OF COMPUTER ARCHITECTURES ”, Facta Universitatis , Ser. Electronics and Energetics, Vol. 17, December 2004, pp. 325-341.
[15] M. Stojcev, T. Tokic, I. Z. Milentijevic : “ THE LIMITS OF SEMICONDUCTOR TECHNOLOGY AND ONCOMING CHALLENGES IN COMPUTER MICROARCHITECTURES AND ARCHITECTURES ”, Facta Universitatis , Ser. Electronics and Energetics, Vol. 17, December 2004, pp. 285-312.
[16] E.I.Milovanovic, M.B.Tošic, I.Ž.Milovanovic, I.Z.Milentijevi c, “DESIGNIING PROCESSOR-TIME OPTIMAL LINEAR SYSTOLIC ARRAYS FOR MATIRX VECTOR MULTIPLICATION”, J. Electrotechn. Math., No.1, pp. 7-19, 1998.
[17] E.I.Milovanovic, M.B.Tošic, I.Ž.Milovanovic, I.Z.Milentijevi c, “DESIGNIING PROCESSOR-TIME OPTIMAL LINEAR SYSTOLIC ARRAYS FOR MATIRX VECTOR MULTIPLICATION”, J. Electrotechn. Math., No.1, pp. 7-19, 1998.
[18] A.Lazrevic, I.Z.Milentijevic , T.I.Tokic, "CONFIGURABLE INDUSTRIAL CONTROLLER - CIC BASED ON THE PIC 16F877", Journal of Electrotechincs and Mathematics , Vol. 5, No. 1, pp. 19-35, 2000.
Conference Papers
[19] I. Milentijevic, V. Ciric, “ Assignment of Folding Sets for Adaptive FIR Filtering on Folded Array ”, Proceedings of the WPS - DSD 2003, 29 th EUROMICRO Conference, Belek, Turkey, September 2003, pp. 21-22.
[20] V. Ciric, I. Milentijevic, “ Configurable Folded Bit-Plane Architecture for FIR Filtering ”, Proceedings of the WPS - DSD 2003, 29 th EUROMICRO Conference, Belek, Turkey, September 2003, pp. 23 -24.
[21] Ivan Milentijevic , Vladimir Ciric , Teufik Tokic and Oliver Vojinovic , “ Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor” , DSD 2002, EUROMICRO Symposium on Digital System Design , Dortmund, Germany, September 2002, pp. 45-52.
[22] I. Milentijevic, I. Nikolic, V. Ciric, O. Vojinovic, and T. Tokic, “ Synthesis of Folded Fully Pipelined Bit-Plane Architecture” , Proc. 22nd International Conference on Microelectronics (MIEL 2002) Vol 2 , Niš, Yugoslavia, May 2002, pp. 683-686.
[23] Vladimir Ciric , Ivan Milentijevic , Oliver Vojinovic , Teufik Tokic, “Family of Folded Bit-Serial Multipliers”, Proc. 6 th International Conference – TELSIKS 2003, Nis, Serbia and Montenegro, October 2003, pp. 614-617.
[24] V. Ciric, I. Milentijevic, O. Vojinovic, “ Retiming and Register Number Minimization for Adaptive FIR Filter Arcitecture ”, Proceedings of a Workshop on Computational Intelligence and Information Technologies, Nis, Serbia and Montenegro, October 2003, pp. 93-96 .
[25] I. Milentijevic, I. Nikolic, O. Vojinovic, V. Ciric and T. Tokic, "FOLDED BIT-PLANE ARCHITECTURES", Proceedings of the Second International Conference on Informatics and Information Technology, 20-23. December 2001, pp. 282-292.
[26] I. Milentijevic, T. Tokic, I. Nikolic, O. Vojinovic and V. Ciric, “ Synthesis of Folded FIR Filter Architecture With Reordered Partial Products” , Proceedings of a Workshop on Computational Intelligence and Informational Technologies , Niš, 20-21. June 2001, pp. 155-160.
[27] I. Milentijevic, V. Ciric, O. Vojinovic, T. Tokic, " SYNTHESIS PROCEDURE FOR FOLDED FIR FILTER ARCHITECTURE WITH CHANGEABLE FOLDING FACTOR", 3 rd Int. Conf. CiiT, Molika, Macedonia, December 2002 , pp. 12-20.
[28] T.Tokic, V. Ciric, I.Milentijevic, O.Vojinovic, "FPGA IMPLEMENTATION OF FOLDED SEMI-SYSTOLIC FIR FILTER WITH CHANGEABLE FOLDING FACTOR", 3 rd Int. Conf. CiiT, Molika, Macedonia, Deecember 2002, pp. 21-30.
[29] I. Milentijevic, V. Ciric , " SYNTHESIS OF COEFFICIENT BIT REORDERING MODULE for FOLDED BIT-PLANE ARRAYS", 4 rd Int. Conf. CiiT, Molika, Macedonia, December 2003, pp. 332-342.
[30] I. Milentijevic, V. Ciric , O. Vojinovic, " FLEXIBLE FOLDED FIR FILTER ARCHITECTURE ", Proc. 24rd International Conference on Microelectronics (MIEL 2004) Vol 2, Niš, Yugoslavia, May 2004, pp. 723-726.
[32] V. Ciric , I. Milentijevic, " COEFFICIENT BIT REORDERING METHOD FOR CONFIGURABLE FIR FILTERING ON FOLDED BIT-PLANE ARRAY ", 8 th EUROMICRO Conference on Digital System Design, Porto, Portugal, September 2005, pp. 135-138.
[33] V. Ciric, I. Milentijevic, "AREA-TIME TRADEOFFS IN H.264/AVC DEBLOCKING FILTER DESIGN FOR MOBILE DEVICES", IEEE Conference on Signal Processing and its Applications, Sharjah, United Arab Emirates, February 2007, (accepted for publication).
[34] I. Milentijevic, V. Ciric, "PROJECT-BASED LEARNING ENVIRONMENT FOR SPECIAL PURPOSE DSP ARCHITECTURES", IEEE Conference on Signal Processing and its Applications, Sharjah, United Arab Emirates, February 2007, (accepted for publication).
[35] I.Z.Milentijevic, I.Ž.Milovanovic, E.I.Milovanovic, “SOLUTIONS FOR CONVOLUTION ON SYSTOLIC ARRAYS FOR MATRIX-VECTOR MULTIPLICATION”, Telsiks '97, Proceedings of Papers , Vol. 1, pp. 275-278, 1997.
[36] I.Ž.Milovanovic, I.Z. Milentijevic, E.I.Milovanovic, “NEW EFFICIENT SYSTOLIC ARRAY FOR MATRIX-VECTOR MULTIPLICATION”, Telsiks '97, Proceedings of Papers, Vol. 1, pp. 271-274, 1997.
[37] M.P.Bekakos, E.I.Milovanovic, I.Ž.Milovanovic, I.Z.Milentijevic, "AN EFFICIENT SYSTOLIC ARRAY FOR MATRIX-VECTOR MULTIPLICATION", Proceedings of the Fourth Hellenic european Conference on Computer Mathematics and its Applications (HERCMA'98), Athens'98, Vol. 1 (E.A.Lipitakis, ed.), Athens, Hellas, pp. 298 - 317, 1998.
[38] I.Z.Milentijevic, D.M.Maksimovic, M.B.Tosic, M.K.Stojcev, "FAULT - TOLERANT SEMI-SYSTOLIC CONVOLVER OF TYPE F BASED ON DIGIT - SERIAL ARITHMETIC", Preprints of Synopsis Papers of 1st Balcan IFAC-type Conf. on Appled Automatic Systems , Ohrid, 27-29. September 1993, pp. 143-144.
[39] I.Z.Milentijevic, I.Z.Milovanovic, E.I.Milovanovic, “SOLUTIONS FOR CONVOLUTION ON SYSTOLIC ARRAYS FOR MATRIX-VECTOR MULTIPLICATION”, Telsiks '97, Proceedings of Papers , Vol. 1, pp. 275-278, 1997.
[40] I.Z.Milovanovic, I.Z. Milentijevic, E.I.Milovanovic, “NEW EFFICIENT SYSTOLIC ARRAY FOR MATRIX-VECTOR MULTIPLICATION”, Telsiks '97, Proceedings of Papers, Vol. 1, pp. 271-274, 1997.